1. Field of the Invention
The present invention relates to a transceiver module for optical communications.
2. Description of Related Art
There have been provided transceiver modules for optical communications which are compliant with the IEEE802.3ae standard, for example. A transceiver compliant with the IEEE802.3ae standard includes, for example, an NV (Non-Volatile) register, a DOM (Digital Optical Monitoring) register, an LASI (Link Alarm Status Interrupt) register, etc. which are XENPAK (common specifications of optical connectors and optical transceivers which operate according to the XAUI (10 Gigabit Attachment Unit Interface) protocol adopted by 10 Gbit Ethernet (registered trademark) defined by the IEEE802.3ae standard) (refer to nonpatent reference 1, for example).
A related art transceiver IC (referred to as a PHY IC from here on) which constitutes such a transceiver module mentioned above has both an IEEE register which is used when carrying out communications processing and an XENPAK register which is defined by the above-mentioned standard, those registers being implemented via hardware. As error-associated registers which belong to those registers, there exist interrelated registers (i.e., LASI_Status registers) holding the same contents in the IEEE registers and XENPAK registers, respectively.
In the related art transceiver module, when a change is made to the structure and function of either the IEEE register or the XENPAK register, it is necessary to perform the design and development of the PHY IC again so that the structure and function of the register meet new specifications.
On the other hand, when the structure and function of the XENPAK register which is built in the PHY IC is software-emulated by a device control unit (referred to as a DCU from here on) which is an IC for controlling the PHY IC and other peripheral functions, the structure and function of the XENPAK register can be changed by changing a software program of the DCU which emulates the structure and function of the XENPAK register.
A problem is however that since the DCU software-emulates the structure and function of the XENPAK register, when a host which is a higher-layer device accesses to the XENPAK register via MDIO, a reply output from the XENPAK register in the existing PHY IC collides (or mingles) with a reply output from an XENPAK register of the DCU which emulates that of the PHY IC.
While information about a high-speed error which is detected only by the PHY IC and which is associated with communications processing is stored in a register to which information about an error that occurs in the XENPAX register of the PHY IC can be set, information about a low-speed error which is detected only by the DCU and which is associated with internal processing is stored in a register to which information about an error that occur in the XENPAK register of the PHY IC can be set. Another problem is therefore that a mismatch occurs between the contents of the register associated with errors (i.e., an LASI_Status register) in the PHY IC and those in the DCU.